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d a t a sh eet product speci?cation supersedes data of april 1988 file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct221 dual non-retriggerable monostable multivibrator with reset for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 features pulse width variance is typically less than 5% pin-out identical to 123 overriding reset terminates output pulse nb inputs have hysteresis for improved noise immunity output capability: standard (except for nr ext /c ext ) i cc category: msi general description the 74hc/hct221 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct221 are dual non-retriggerable monostable multivibrators. each multivibrator features an active low-going edge input (n a) and an active high-going edge input (nb), either of which can be used as an enable input. pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. schmitt-trigger input circuitry for the nb inputs allow jitter-free triggering from inputs with slow transition rates, providing the circuit with excellent noise immunity. once triggered, the outputs (nq, n q) are independent of further transitions of n a and nb inputs and are a function of the timing components. the output pulses can be terminated by the overriding active low reset inputs (n r d ). input pulses may be of any duration relative to the output pulse. pulse width stability is achieved through internal compensation and is virtually independent of v cc and temperature. in most applications pulse stability will only be limited by the accuracy of the external timing components. the output pulse width is defined by the following relationship: t w =c ext r ext in 2 t w = 0.7c ext r ext pin assignments for the 221 are identical to those of the 123 so that the 221 can be substituted for those products in systems not using the retrigger by merely changing the value of r ext and/or c ext . quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i +? (c l v cc 2 f o ) + 0.33 c ext v cc 2 f o + d 28 v cc where: f i = input frequency in mhz; f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c ext = timing capacitance in pf; c l = output load capacitance in pf v cc = supply voltage in v; d = duty factor in % 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v symbol parameter conditions typical unit hc hct propagation delay c l = 15 pf; v cc =5 v; r ext =5 k w ; c ext = 0 pf t phl n a, nb, n r d to nq, n q 2932ns t plh n a, nb, n r d to nq, n q 3536ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 90 96 pf
december 1990 3 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 ordering information see 74hc/hct/hcu/hcmos logic package information . pin description pin no. symbol name and function 1, 9 1 a, 2 a trigger inputs (negative-edge triggered) 2, 10 1b, 2b trigger inputs (positive-edge triggered) 3, 11 1 r d , 2 r d direct reset inputs (active low) 4, 12 1 q, 2 q outputs (active low) 72r ext /c ext external resistor/capacitor connection 8 gnd ground (0 v) 13, 5 1q, 2q outputs (active high) 14, 6 1c ext , 2c ext external capacitor connection 15 1r ext /c ext external resistor/capacitor connection 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 fig.4 functional diagram. function table notes 1. h = high voltage level l = low voltage level x = dont care - = low-to-high level = high-to-low level = one high-level output pulse = one low-level output pulse 2. if the monostable was triggered before this condition was established the pulse will continue as programmed. 3. for this combination the reset input must be low and the following sequence must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9) must be low and pin 2 (or 10) set high. now the reset input goes from low-to-high and the device will be triggered. inputs outputs n r d n anbnqn q lxxlh xhxl (2) h (2) xx ll (2) h (2) hl - h h - lh (3) (3)
december 1990 5 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 note it is recommended to ground pins 6 (2c ext ) and 14 (1c ext ) externally to pin 8 (gnd). fig.5 logic diagram. fig.6 timing component connections.
december 1990 6 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard (except for nr ext /c ext ) i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min typ max. min max. min. max. t plh propagation delay (trigger) n a, nb to nq 72 26 21 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 c ext = 0 pf; r ext =5 k w ; fig.10 t plh propagation delay (trigger) n r d to nq 80 29 23 245 49 42 305 61 52 370 74 63 ns 2.0 4.5 6.0 c ext = 0 pf; r ext =5 k w ; fig.10 t phl propagation delay (trigger) n a, nb to n q 58 21 17 180 36 31 225 45 38 270 54 46 ns 2.0 4.5 6.0 c ext = 0 pf; r ext =5 k w ; fig.10 t phl propagation delay (trigger) n r d to n q 63 23 18 195 39 33 245 49 42 295 59 50 ns 2.0 4.5 6,0 c ext = 0 pf; r ext =5 k w ; fig.10 t plh propagation delay (reset) n r d to n q 66 24 19 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 c ext = 0 pf; r ext =5 k w ; fig.11 t plh propagation delay (reset) n r d to nq 58 21 17 180 36 31 225 45 38 270 54 46 ns 2.0 4.5 6.0 c ext = 0 pf; r ext =5 k w ; fig.11 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.10 t w trigger pulse width n a = low 75 15 13 25 9 7 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.7 t w trigger pulse width nb = high 90 18 15 30 11 9 115 23 20 135 27 23 ns 2.0 4.5 6.0 fig.7 t w trigger pulse width n r d = low 75 15 13 25 9 7 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.8 t w output pulse width n q = low nq = high 630 700 770 602 798 595 805 m s 5.0 c ext = 100 nf; r ext = 10 k w ; fig.10
december 1990 7 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 t w output pulse width nq or n q 140 -- ns 2.0 4.5 6.0 c ext = 28 nf; r ext =2 k w ; fig.10 t w output pulse width nq or n q 1.5 -- m s 2.0 4.5 6.0 c ext = 1 nf; r ext =2 k w ; fig.10 t w output pulse width nq or n q 7 -- m s 2.0 4.5 6.0 c ext = 1 nf; r ext = 10 k w ; fig.10 t w pulse width match between circuits in the package 2 -- % 4.5 to 5.5 c ext = 1000 pf; r ext = 10 k w t rem removal time n r d to n a or nb 100 20 17 30 11 9 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.9 r ext external timing resistor 10 2 1000 1000 - - - - k w 2.0 5.0 fig.12 fig.13 c ext external timing capacitor no limits pf 2.0 5.0 fig.12 fig.13 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min typ max. min max. min. max.
december 1990 8 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard (except for nr ext /c ext ) i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient nb 0.30 n a 0.50 n r d 0.50
december 1990 9 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min typ max min max. min. max. t plh propagation delay (trigger) n a, n r d to nq 30 50 63 75 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.10 t plh propagation delay (trigger) nb to nq 24 42 53 63 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.10 t phl propagation delay (trigger) n a to n q 26 44 55 66 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.10 t phl propagation delay (trigger) nb to n q 21 35 44 53 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.10 t phl propagation delay (trigger) n r d to n q 26 43 54 65 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.10 t phl propagation delay (reset) n r d to nq 26 43 54 65 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.11 t plh propagation delay (reset) n r d to n q 31 51 64 77 ns 4.5 c ext = 0 pf; r ext =5 k w ; fig.11 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.10 t w trigger pulse width n a = low 20 13 25 30 ns 4.5 fig.10 t w trigger pulse width nb = high 20 13 25 30 ns 4.5 fig.10 t w pulse width n r d = low 22 13 28 33 ns 4.5 fig.8 t w output pulse width n q = low nq = high 630 700 770 602 798 595 805 m s 5.0 c ext = 100 nf; r ext = 10 k w ; fig.10 t w trigger pulse width nq or n q 140 -- ns 4.5 c ext = 28 pf; r ext =2 k w ; fig.10 t w trigger pulse width nq or n q 1.5 -- m s 4.5 c ext = 1 nf; r ext = 2 k w ; fig.10
december 1990 10 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 t w trigger pulse width nq or n q 7 -- m s 4.5 c ext = 1 nf; r ext = 10 k w ; fig.10 t rem removal time n r d to n a or nb 20 12 25 30 ns 4.5 fig.9 r ext external timing resistor 2 1000 -- k w 5.0 fig.13 c ext external timing capacitor no limits pf 5.0 fig.13 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min typ max min max. min. max.
december 1990 11 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 ac waveforms fig.7 output pulse control; n r d = high. fig.8 output pulse control using reset input n r d ; n a = low. fig.9 waveforms showing the removal times; n r d to n a or nb. (1) hc : v m =v m = 50%; v i = gnd to v cc . hct : v m =v m = 1.3 v; v i = gnd to 3 v. fig.10 waveforms showing the triggering of one shot by input n a or input nb for one period (t w ) and minimum pulse widths of the trigger inputs n a and nb. (1) hc : v m =v m = 50%; v i = gnd to v cc . hct : v m =v m = 1.3 v; v i = gnd to 3 v. fig.11 waveforms showing the reset to nq and n q output propagation delays. (1) hc : v m =v m = 50%; v i = gnd to v cc . hct : v m =v m = 1.3 v; v i = gnd to 3 v.
december 1990 12 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 fig.12 hc typical output pulse width as a function of timing capacitance (v cc = 2 v).
december 1990 13 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 fig.13 hc/hct typical output pulse width as a function of timing capacitance (v cc = 4.5 v).
december 1990 14 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 fig.14 hc typical output pulse width as a function of timing capacitance (v cc = 6 v).
december 1990 15 philips semiconductors product speci?cation dual non-retriggerable monostable multivibrator with reset 74hc/hct221 fig.15 typical output pulse width as a function of temperature; c x = 0.1 m f; r x =10k w ; v cc =5v. fig.16 k factor as a function of supply voltage; r x =10k w ;t amb =25 c. power-down consideration a large capacitor (c x ) may cause problems when powering-down the monostable due to the energy stored in this capacitor. when a system containing this device is powered-down or a rapid decrease of v cc to zero occurs, the monostable may substain damage, due to the capacitor discharging through the input protection diodes. to avoid this possibility, use a damping diode (d x ) preferably a germanium or schottky type diode able to withstand large current surges and connect as shown in fig.17. fig.17 power-down protection circuit. package outlines see 74hc/hct/hcu/hcmos logic package outlines .

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